1. Field of the Invention
Embodiments of the invention relates to a display device, and more particularly, to a flat panel display device. Although embodiments of the invention are suitable for a wide scope of applications, they are particularly suitable for obtaining a chip on glass (“COG”) display device that transmits the same voltage level signal to drive integrated circuits (“ICs”).
2. Discussion of the Related Art
Flat panel display (“FPD”) devices having portability and low power consumption have been a subject of recent researches in the coming of the information age. Among the various types of FPD devices, liquid crystal display (“LCD”) devices are widely used as monitors for notebook computers and desktop computers because of their high resolution, ability to display colors and superiority in displaying moving images.
In general, an LCD device includes two glass substrates and a liquid crystal layer between the two glass substrates. The LCD device uses the optical anisotropy and polarization properties of liquid crystal molecules to produce an image. Due to the optical anisotropy of the liquid crystal molecules, refraction of light incident onto the liquid crystal molecules changes with the alignment direction of the liquid crystal molecules. The liquid crystal molecules have long thin shapes that can be aligned along specific directions, and the alignment direction of the liquid crystal molecules can be controlled by applying an electric field. Accordingly, the alignment of the liquid crystal molecules changes in accordance with the direction of the applied electric field. Thus, by properly controlling the electric field applied to a group of liquid crystal molecules within respective pixel regions, a desired image can be produced by appropriately modulating transmittance of the incident light. For example, an active matrix type LCD device using a thin film transistor as a switching element has been widely used to display a dynamic image.
FIG. 1 is a schematic view showing a liquid crystal display device having an LCD panel and a driving circuit unit according to the related art, and FIG. 2 is a schematic plan view of the LCD panel shown in FIG. 1. In FIG. 1, an LCD device includes an LCD panel 2 and a driving circuit unit 26. The driving circuit unit 26 includes an interface 10, a timing controller 12, a source voltage generation unit 14, a reference voltage generation unit 16, a source driver 18 and a gate driver 20.
The interface 10 receives data signals, such as red (R), a green (G) and blue (B) data, and control signals, such as an input clock, a horizontal synchronizing signal, a vertical synchronizing signal, and a data enable signal, from a driving system, such as a personal computer. The interface 10 then provides the data and control signals to the timing controller 12. The timing controller 12 then supplies the data and control signals to drive the source and gate drivers 18 and 20, respectively. Generally, a low voltage differential signal (“LVDS”) interface or a time to live (“TTL”) interface is utilized to transmit the data and control signals from the driving system. Further, the interface 10 and the timing controller 12 may be formed on a single chip.
As shown in FIG. 2, the LCD panel 2 includes a plurality of gate lines GL1 . . . GLn, and a plurality of data lines DL1 . . . DLm on a first substrate (not shown). A plurality of pixel regions P are defined by the crossing of the gate and data lines GL1 . . . GLn and DL1 . . . DLm. A thin film transistor TFT is formed at each crossing of the gate and data lines GL1-GLn and DL1 . . . DLm. In addition, a pixel electrode (not shown) is formed electrically connected to the thin film transistor TFT. Although not shown, a second substrate faces the first substrate and has a color filter and a common electrode formed thereon. Further, a liquid crystal layer may be interposed between the first and second substrates. The liquid crystal layer is driven by a vertical electric field between the pixel electrode and the common electrode, thereby displaying an image.
The timing controller 12 generates a control signal for driving the gate driver 20 and the source driver 18 using the control signal inputted through the interface 10. The gate driver 20 includes a plurality of gate driver ICs (not shown), and the source driver 18 includes a plurality of source driver ICs (not shown). Further, the inputted data through the interface 10 is transmitted to the source driver 18.
The reference voltage generation unit 16 generates a reference voltage of a digital to analog converter (“DAC”) utilized in the source driver 18. The reference voltage is determined by a producer with respect to a transmittance-voltage (T-V) property of the LCD panel 2. The source driver 18 selects the reference voltage of the inputted data by responding to the inputted control signals from the timing controller 12, and a rotation angle of the liquid crystal molecule is controlled by providing the selected reference voltage to the LCD panel 2.
The gate driver 20 performs an ON/OFF control of the thin film transistors TFT arranged on the LCD panel 2 by responding to the control signals inputted from the timing controller 12. In particular, by sequentially enabling the gate lines GL1 . . . GLn by the required time for one horizontal synchronizing, the thin film transistors TFT are sequentially driven by one line to allow analog signals provided from the source driver 18 to be applied to the pixel electrodes to the thin film transistors TFT along the driven line.
Generally, the source driver 18 and the gate driver 20 include a plurality of chips. The source voltage generation unit 14 provides the LCD panel 2 with an operation source of respective elements. Further, the source voltage generation unit 14 generates and provides the LCD panel 2 with a voltage of a common electrode of the LCD panel 2. Also, although not shown, the LCD device further includes a backlight unit including a lamp to provide light onto the LCD panel 2.
Recently, a chip on glass (COG) type LCD device is suggested as a large size model that is in high demand by users. In the COG type LCD device, the drive IC chip is directly packaged on the LCD panel 2 to obtain a fine pitch, an ultra-thin and a light weight type model and the like. FIG. 3 is a schematic plan view showing a chip on glass (“COG”) type LCD panel according to the related art, and FIG. 4 is an expanded view of a region “IV” of the COG type LCD panel shown in FIG. 3.
In FIG. 3, first to fourth source drive ICs S1 . . . S4 and first and second gate drive ICs G1 and G2 are packaged on an array substrate of an LCD panel 40 in a non-display region. The non-display region is along a periphery of an active area AA of the LCD panel 40. Each of the first to fourth source drive ICs S1 . . . S4 and each of the first and second gate drive ICs G1 and G2 receive signals from a circuit board 55. The circuit board includes a flexible printed circuit (“FPC”) formed at an edge of the LCD panel 40.
However, although each of the first to fourth source drive ICs S1 . . . S4 spaced apart from the circuit board 55 with the same distance as each other directly receives the signals from the circuit board 55, the first and second gate drive ICs G1 and G2 spaced from the circuit board 55 at different distances. In particular, since the second gate drive IC G2, which is spaced further away from the first gate drive IC G1, the first gate drive IC G1 becomes a signal transmission means to the second gate drive IC G2 and the second gate drive IC G2 receives signals that are transmitted through the first gate drive IC G1.
As shown in FIG. 4, each of the first and second gate drive ICs G1 and G2 has a gate high signal terminal VGH and a gate low signal terminal VGL. The gate high signal terminal VGH and the gate low signal terminal VGL of the first gate drive IC G1 respectively face the gate high signal terminal VGH and the gate low signal terminal VGL of the second gate drive IC G2. A high signal line 60a is disposed between the gate high signal terminals VGH of the first and second drive ICs G1 and G2 to transmit the gate high signal SVGH from the first gate drive IC G1 to the second gate drive IC G2. Similarly, a low signal line 60b is disposed between the gate low signal terminals VGL of the first and second drive ICs G1 and G2 to transmit the gate low signal SVGL from the first gate drive IC G1 to the second gate drive IC G2. As a result, the gate high signal SVGH and the gate low signal SVGL transmitted to the second gate drive IC G2 is substantially not equal to the gate high signal SVGH and the gate low signal SVGL transmitted from the circuit board 55 due to the declination of the input signals between the first and second drive ICs G1 and G2.
Accordingly, when the first gate drive IC G1 is utilized as a signal transmission means for the second gate drive IC G2, there is a problem that the voltage level of the signal applied to the first gate drive IC G1 and the voltage level of the signal applied to the second gate drive IC G2 are different from each other. In other words, the voltage of the gate high signal SVGH and the gate low signal SVGL received by the first gate drive IC G1, which are directly inputted from the circuit board 55, are different from the voltage of the gate high signal SVGH and the gate low signal SVGL received by the second drive IC G2. In addition, signal attenuation occurs due to the transmission through the first gate drive IC G1 and due to the resistance of a signal line 60 including the high signal line 60a and the low signal line 60b. 
The signal attenuation of the signal line 60 leads respective gate drive ICs G1 and G2 to transmit the different voltage levels to the gate lines. As a result, a screen division phenomenon occurs where a display image includes a gate block dim due to a brightness difference between a portion of the display region controlled by the first gate drive IC G1 and a portion of the display region controlled by the second gate drive IC G2.